(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of adjusting NMOS spacer width after PMOS formation to achieve reliable devices in the manufacture of integrated circuits.
(2) Description of the Prior Art
The requirements of shorter spacer width for NMOS devices and longer spacer width for PMOS devices becomes important for deep-submicron devices. As a result, NMOS devices can provide a higher driving current and PMOS devices can have a wider process margin. Some workers in the field have used double or differential spacer techniques in LDD structure. The material used for the double spacer may be polysilicon, as taught in the paper, "High Drivability and High Reliability MOSFETs with Non-Doped Poly-Si Spacer LDD Structure," by A. Shimizu et al, Symposium of VLSI Technology, 1992, pp. 90-91, or the material may be an oxide film, as taught in the paper, "Double Spacer Technique for Titanium Self-Aligned Silicidation Technology," by W. D. Su et al, Symposium of VLSI Technology, 1991, pp. 113-116. However, these processes are complicated in terms of chemical vapor deposition and cycle time.
U.S. Pat. No. 4,760,033 to Mueller teaches a process of using different N and P MOS spacer widths for reducing the under-diffusion of the implanted source-drain regions under the gate areas. U.S. Pat. No. 5,091,763 to Sanchez discloses the use of a conductive spacer coupled with a thin oxide spacer in order to form self-aligned source and drain regions.
NMOS source/drain implantation is commonly performed prior to PMOS because of the fast diffusion of boron, which is typically used for the PMOS implantation. However, if no thermal processing is performed between the two implantations which would drive in the boron, the NMOS and PMOS implantations can be reversed. Therefore, the NMOS spacer width can be adjusted by etching after PMOS source/drain formation.